In recent years, a stacked type semiconductor memory device has been proposed in which memory cell transistors are integrated three-dimensionally. In such a stacked type semiconductor memory device, a stacked body in which electrode films and insulating films are stacked alternately is provided on a semiconductor substrate; and semiconductor pillars that pierce the stacked body are provided. The memory cell transistors are formed at each crossing portion between the electrode films and the semiconductor pillars. Data is stored by changing thresholds of the memory cell transistors; and the data is read by determining the thresholds of the memory cell transistors. For such a stacked type semiconductor memory device, it is predicted that the on-current of the read operation will decrease and it will be difficult to read the data as the semiconductor pillars are downscaled to increase the integration.